PCB wiring layer planning

1, the number of layers of signal planning

Wiring channel is usually the important factor to determine the number of signal layers. The first to know whether there is a deep plate BGA and connectors, BGA depth and PIN BGA spacing is the key to determine the BGA outlet layer. For example, BGA 1.0mm through the hole between the two lines can generally be over, BGA 0.8mm across the hole can only be a line between the two outlet layer there is a big difference. The connector is mainly considering the depth between two through holes through a pair of differential lines.

  Two over the hole can only lead a line between the BGA outlet, sharing the 4 layer.

  Two can pass through the hole between the lines of the BGA outlet, sharing the 2 layer.

Secondly to consider in high-speed signal wiring channel, because of the high speed signal processing requirements more and need to consider stub, line spacing and the reference level and other factors, so it is necessary to give priority to the wiring channel is enough.


  Fly line for high speed signal

Finally, the planning of the bottleneck area, after the basic layout of the treatment, for the relatively narrow bottleneck areas need to focus on. Considering almost to the junction, sensitive signal line, a special signal topology specific computational bottleneck area up to the line number, how many layers to make need of all lines through the region.


2, power, ground level of planning

The number of layers of the power supply is mainly determined by the number of types, distribution, capacity, performance index of the single board and the cost of the single board. Power plane settings need to meet the two conditions: the power supply is not staggered; to avoid the adjacent layer important signal cross segmentation.

Layer settings need to pay attention to the following points: the second layer to have relatively complete horizon in the face of main devices; high speed, high frequency, clock signal to reference plane; main power and ground planes are tightly coupled, reduce power plane impedance and so on.

Comprehensive consideration of the above two points, basically there is no part of the line can not go through, temporary plus layer, and then large-scale changes, a waste of time costs occur. In our actual evaluation, we may also need to consider the impact of processing, plate thickness, etc..


(Source: Inside information)

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