Three major trends in PCB design with Allegro/OrCAD 16.6

    Cadence recently announced the launch of the latest version of the PCB solution Allegro/OrCAD 16.6. VAR&SPB Department of the company's China Sales Manager Xiong Wen said that the new version in response to the miniaturization of PCB design, high speed, intelligent, and enhance the efficiency of collaborative design team to achieve great progress.

     "Protel provides a complete design toolkit, Allegro tool provides a flexible configuration, through the split into many function modules, the different needs of customers to find the most appropriate solution, thus greatly saving cost." Xiong Wen said, in addition, Cadence is still Design Team, miniaturization, three-dimensional interface and other aspects of the optimization, and strengthen the user interactive features, engineers can be designed by cloud storage will be designed into the cloud."

     For example, the miniaturization of modified Allegro 16.6 new features to help embedded double and vertical component, through the improvement and implementation of timing sensitive physical verification, timing closure to speed up the 30-50% high-speed interface, and improved ECAD and mechanical CAD (MCAD) and OrCAD collaborative design; 16.6 PSpice is not only the introduction of a number of nuclear simulation support system, but also by improving the simulation set and the average increase of 20%, the simulation speed to speed up the vital multifunctional electronic product development.

     Analysis of Comtech Cadence Product Manager Wang Qiping said that the main challenges facing the PCB design from the following 4 aspects: 1 low cost. Product functions more and more, but the number of PCB boards, area and wiring is getting less and less; 2 high speed. Mobile phone, tablet PC SoC processor frequency has reached the RF level of 1.6GHz, but also to consider the impact of DDR2/3/4; 3 miniaturization of the signal integrity of the challenge. Cadence 2012 was the acquisition of the signal and power integrity technology supplier Sigrity, is hoping to further enhance the ability to simulate; 4 how to make design tools intelligent, to accelerate the product market cycle. Therefore, it is very necessary to make an in-depth understanding of the engineers how to combine the advantages of Allegro 16.6 with the local needs, so as to bring the optimization design.

     Specifically, Allegro 16.6 to speed up the implementation of timing sensitive physical by automatic interaction delay adjustment (AiDT). Automatic interactive delay adjustment can shorten the time, meet the timing constraints advanced standard interface, such as DDR3; in addition, AiDT can also help users to quickly adjust the key interface by high speed signal time, or applied to the byte channel level, PCB will be on the line to adjust the time from days to hours shortened. Timing Designer Allegro combined with PCB SI EMA function, to help users quickly realize the key high speed signal timing closure.

     Allegro suite PCB miniature design function launched in 2011, new products will continue to use the production process of active and passive components embedded in the latest, shrinking the size of the circuit board to solve specific design issues related to. Components can be used to sneak into the Z axis perpendicular to the PCB layer, resulting in a substantial reduction in X and Y axis wiring space. At the same time, PCB/enclosure design is simplified through the ECAD-MCAD process, proStep iViP standard EDMD schema 2 based version, to reduce unnecessary iterations between the ECAD and the MCAD team, shorten product development time.

     The OrCAD version of the 16.6 version of the new integrated signal integrated flow provides a seamless bi-directional interface between Capture OrCAD and PCB SI OrCAD products. This new integrated implementation of the simplified pre wiring topology and constraints of the development of automated and comprehensive design methods to improve the productivity of 100%. OrCAD 16.6 at the same time also extends the Tcl programming functions and Capture PSpice to OrCAD application methods. Thus, the user can extend and customize their simulations and environments in the standard "take and take" solution to the extent that the solution can provide. By calling the Tcl simulation data and environment, the user can customize the equation and the equation to customize the user to allow any parameters, map user parameters or PSpice program simulation.

     Wang Qiping said, the market resources and the joint support is an important advantage of Comtech, Comtech can provide users with good support from the chip level to the board level, but also more competitive in terms of cost. In 2012, the volume of business agent Comtech Cadence achieve the nearly 100% growth in the number of customers has reached more than and 100 within two years. From an existing example, the customer with two months to complete all of the switch from Protel to Cadence tool.


 

(Source: Inside information)

Quick Contact

Contact Information

Bantian Group Commercial Center building, Dafapu Rd, Bantian, Longgang district, Shenzhen 518125, China.

+86-755-27530105

sales03@zitrok.com

SOCIALS

Message Board